Circuit for processing data signals

ABSTRACT

The invention relates to a circuit arrangement which includes a stage for the processing of data signals which are applied to the stage in a selectable sequence during time intervals defined by a clock signal. 
     In order to construct a circuit arrangement of this kind in such a manner that the power consumption which is dependent on the data signals is disguised, the invention proposes to supply the circuit arrangement, with modified data signals, instead of the data signals to be processed, in a respective part of each time interval.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a circuit arrangement which includes a stagefor the processing of data signals which are applied to the stage in aselectable sequence during time intervals which are defined by a clocksignal.

2. Description of the Related Art

Circuit arrangements of this kind are used in a wide variety of digitalswitching circuits which process data. Notably when such circuitarrangements, or their elements, are constructed while using CMOScircuits their current consumption can be strongly reduced, because suchCMOS circuits, and gates constructed using such circuits, consumecurrent only when value of the data signals occurring therein changes.Consequently, the current consumption of a circuit arrangement thusconstructed is dependent on the changes of the data signals. This couldmake it possible to extract information as regards the changes of thedata, and hence as regards the data themselves, from the variation intime of the current consumption. Such information, however, should notbe surrendered, notably not in the case of data signals which are to bekept secret.

This problem becomes acute when parts of synchronously operating logiccircuits are clocked only conditionally in order to save current, i.e.only when the relevant circuit element is indeed used for the currentdata signal processing. It is exactly this aim to minimize the currentconsumption that makes dependencies of the current consumption on thedata signals particularly noticeable. Such switching circuits exhibitdistinct dependencies of the electrical power consumption on theprocessed data signals.

SUMMARY OF THE INVENTION

It is an object of the invention to construct a circuit arrangement ofthe kind set forth in such a manner that the dependency of the powerconsumption on the data signals is disguised.

This object is achieved in a circuit arrangement of the kind set forthin that in a respective part of each time interval the circuitarrangement is supplied with modified data signals instead of the datasignals to be processed.

In accordance with the invention, the described circuit arrangement isthus supplied with other, as different as possible data beforeprocessing the actually intended data. It can thus be achieved that thenumber of switching operations in the circuit arrangement isapproximately the same in each time interval, irrespective of whetherand how much the data signals to be actually processed change and whatvalues they assume. This results in a power consumption which can nolonger be correlated with the processing of the actual data signals.

The invention offers the advantage that the same circuit arrangement isused for the actual task, i.e. for the data signals to be actuallyprocessed, as well as for causing an additional current consumption bythe processing of modified data signals which have an apparent meaningonly. This takes place in a kind of time multiplex in each of the timeintervals. More specifically, a dummy operation without meaning and theoperation involving the actual data signals to be processed are thusperformed sequentially.

When the time intervals are defined, for example by a square-wave clocksignal, the modified data signals can be processed in a respective halfperiod of the clock signal and the data signals to be actually processedin the respective other half period of the clock signal. The modifieddata signals, however, can also be supplied and processed in timeintervals which are short in comparison with the period of the clocksignal and are situated at the area of, for example the edges of theclock signal, whereas the data signals to be actually processed aresupplied during the remaining time intervals of the periods of the clocksignal.

The invention achieves a very effective disguise while using very fewcircuit means. This is realized at the expense of a slightly increasedcurrent consumption.

Preferably, the modified data signals are derived from the data signalsto be actually processed by means of a data modification device which iscontrolled by the clock signal and can be simply inserted in the pathsfor the data signals. Preferably, such a data modification deviceincludes an exclusive-OR circuit or a multiplexer device. A preferredembodiment of the circuit arrangement according to the inventionincludes a combinatory logic circuit which is inserted in the stage forthe processing of the data signals. This combinatory logic circuit maybe connected so as to precede the data modification device. The datasignals to be processed can be applied from a first storage device tothe combinatory logic circuit via the data modification device, the datasignals formed in the combinatory logic circuit being applied to asecond storage device so as to be stored.

Particularly advantageous is the use of the circuit arrangementaccording to the invention in combination with CMOS circuits. Theapplication, however, is in principle not restricted to such circuits.

Disguising is achieved notably in that the combinatory logic circuitmust process new data signals in each time interval, i.e. in that thesedata signals change under the influence of the data modification device.This precludes pronounced differences in the power consumption of thecircuit arrangement for different time intervals, which differencescould arise, for example, when the data signals to be processed containvery few changes only.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings show an embodiment of the invention which will be describedin detail hereinafter.

FIG. 1 shows a block diagram of an embodiment of the present invention.

FIGS. 2 and 3 show aspects of the data modification device for theembodiment shown in FIG. 1.

FIGS. 4A-4E show a number of signal variations in the circuitarrangement shown in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The circuit arrangement shown in FIG. 1 includes a first storage devicewhich consists of two D-flipflops 1, 2 whose data inputs 3, 4 receivethe data signals to be processed. A clock signal is supplied from aclock signal terminal 7 via clock inputs 5, 6. The data signals to beprocessed, stored in the first storage device 1, 2, are output via dataoutputs 8, 9.

From the data outputs 8, 9 the data signals to be processed reach, via adata modification device 10 and leads 11 and 12, respectively, acombinatory logic circuit 13 and from the outputs 14, 15 thereof theyare applied to a second storage device which includes two D-flipflops16, 17. The D-flipflops 16, 17 also receive the clock signal from theclock signal terminal 7 via clock inputs 18, 19. They output the storeddata signals via data outputs 20 and 21, respectively.

FIG. 2 shows a first embodiment of the data modification device 10. Itincludes exclusive-OR gates 22 and 23 which are connected between one ofthe data outputs 8 and 9 and a respective one of the leads 11 and 12.Via each of the exclusive-OR gates 22,23 one of the data signals isconducted from the first storage device 1,2 to the combinatory logiccircuit 13. A second input of each exclusive-OR gate 22,23 is connectedto the clock signal terminal 7. As a result, the modified data signalsare generated by means of the clock signal in each half period. The datasignals on the leads 11, 12, and hence on the outputs 14, 15 of thecombinatory logic circuit 13, thus are first modified at the beginningof each clock signal period and the data signals to be actuallyprocessed are transferred only in the second part of the clock signalperiod. The embodiment shown in FIG. 2 is notably constructed in such amanner that the exclusive-OR gates 22,23 invert the data signals,supplied via the data outputs 8,9 of the first storage device 1,2 in thecase of a high level on the clock signal terminal 7 and conducts thesesignals without modification in the case of a low level on the clocksignal terminal 7.

The data modification device 10 in a second embodiment includes four ANDgates 24, 25, 26 and 27, two OR gates 28 and 29 and an inverter 30. Afirst input of the first and of the third AND gate 24, 26 is connectedto the data output 8. A first input of the second and of the fourth ANDgate 25, 27 is connected to the data output 9. A second input of thefirst and of the fourth AND gate 24, 27 is connected to the output ofthe inverter 30 and the input of the inverter 30 is connected to theclock signal terminal 7 and to a second input of the second and of thethird AND gate 25, 26. The outputs of the first and the second AND gate24, 25 are connected to a respective input of the first OR gate 28 whoseoutput is connected to the lead 11. Analogously, the outputs of thethird and the fourth AND gate 26, 27 are connected to inputs of thesecond OR gate 29 whose output is connected to the lead 12. Themultiplexer arrangement thus formed permutates the data signals from thedata outputs 8, 9 in the case of a high level on the clock signalterminal 7.

FIG. 4 shows, by way of example, some signal variations illustrating theoperation of the circuit arrangements shown in the FIGS. 1 to 3. FIG.4a) shows a square-wave clock signal with a mark-space ratio 1. FIG. 4b)shows, by way of shading, the parts of the clock signal periods duringwhich the data modification devices shown in the FIGS. 2 and 3 perform apermutation or modification of the data signals. Therein, each clocksignal period commences with an ascending edge of the clock signal shownin FIG. 4a).

FIG. 4c) shows a clock signal with a mark-space ratio smaller than 1.For example, this clock signal can be derived from the clock signalshown in FIG. 4a). When such a clock signal is used to control a datamodification device as shown in the FIGS. 2 or 3, the modified datasignals will be generated in the parts of the clock signal periods whichare denoted by shading in FIG. 4d). These parts have been shortenedrelative to those shown in FIG. 4b) so that, for example, in each clocksignal period the combinatory logic circuit 13 has a longer period oftime available for the processing of the data signals to be actuallyprocessed.

In third example a short period of time within which the data signalsare modified can be formed for each edge of the clock signal shown inFIG. 4a). This is symbolically represented in FIG. 4e).

What is claimed is:
 1. A circuit arrangement which includes a stage forthe processing of data signals which are applied to the stage in aselectable sequence during time intervals which are defined by a clocksignal, wherein in a respective part of each time interval the circuitarrangement is supplied with modified data signals instead of the datasignals to be processed, wherein the modified data signals are suppliedonly to mask power consumption of the data signals to be processed.
 2. Acircuit arrangement as claimed in claim 1, further comprising a datamodification device which is controlled by the clock signal and servesto generate the modified data signals from the supplied data signals. 3.A circuit arrangement as claimed in claim 2, characterized in that thedata modification device includes an exclusive-OR circuit.
 4. A circuitarrangement as claimed in claim 2, characterized in that the datamodification device includes a multiplexer device.
 5. A circuitarrangement as claimed in claim 1, characterized in that the stage forthe processing of data signals includes a combinatory logic circuit. 6.A circuit arrangement as claimed in claim 2 further comprising a firststorage device wherefrom the data signals are applied, via the datamodification device, to a combinatory logic circuit, as well as a secondstorage device for the storage of data signals output by the combinatorylogic circuit.
 7. A circuit arrangement as claimed in claim 1 which isconstructed from CMOS circuits.